Multi Core Processing for Software Radio Channel Decoder

The growing number of transmission standards and technologies leads to an increased interest in software defined radios (SDRs). To provide the required computing power for these SDRs, multi processor architectures are considered as a realistic approach. To achieve an optimum speedup, the algorithmic descriptions of the digital baseband processing tasks have to be adequate for these architectures. In this work two approaches for parallel Viterbi decoding on a symmetric multi processor platform are presented, which are based on segmentation of the code trellis in state and time direction. The resulting speedup of these approaches is evaluated on an ARMMPCore platform.